Memory system--cache

Memory system--cache

1. Cache (high-speed buffer memory)

1.1. Basic concepts

  • Cache memory is a primary memory located between the main memory and the CPU. It is composed of static memory chips (SRAM). It has a relatively small capacity and a much higher speed than the main memory. It is close to the speed of the CPU and has a higher unit cost than memory. Cache stores data that frequently accesses memory

1.2. Cache principle, hit rate, failure rate

  • The main basis for using Cache to improve system performance is the principle of program locality

  • Hit rate, failure rate

    • The access hit rate of Cache is h (usually 1-h is the failure rate of Cache), the access cycle time of Cache is t1, and the access cycle time of main memory is t2, then the average access time of the entire system is: t3=hx t1 + (1-h) x t2

1.3. Cache memory mapping mechanism

  • The address allocated to the Cache is stored in an associative memory (CAM). When the CPU makes a memory access request, it will first let the CAM determine whether the data to be accessed is in the Cache, and use it directly if it hits. The process of this judgment is Cache address mapping, and this speed should be as fast as possible

  • Common mapping methods are:

    • Direct mapping
    • Fully associative mapping
    • Group associative mapping
  • Direct mapping

    • It is a many-to-one mapping relationship, but a main memory block can only be copied to a specific location in the Cache
    • Cache row number i and main memory block number j have a functional relationship: i = j% m (where m is the total number of Cache rows)
  • Fully associative mapping

    • Any main memory block in the main memory can be mapped to any row in the Cache (the capacity of the main memory block is equal to the capacity of the Cache row)
    • The Cache page number cannot be extracted directly according to the main memory address. Instead, the main memory block mark and the mark of each Cache page need to be compared one by one to find the page with the mark directly (access to the Cache hit), or there is still no mark after all comparisons are completed. (Failed to access Cache)
    • The main memory block mark is compared with the mark of each Cache page one by one, so this mapping method is very slow and loses the function of the cache. At this time, the biggest disadvantage of the fully associative mapping method. If the homepage mark is compared with each Cache mark at the same time, the cost is too high
  • Group associative mapping

    • It is a compromise between the first two methods. It regroups the blocks in the Cache. The groups are directly mapped, and the blocks in the group are fully associative.
    • Main memory address = area code + group number + block number in the group + address number in the block

1.4.Cache elimination algorithm

  • When the Cache data is full and a miss occurs, some old data must be eliminated, and some new data will be updated to enter the Cache. The way to choose which data to eliminate is to eliminate the algorithm. There are three common methods:

    • Random elimination algorithm
    • First-in-first-out elimination algorithm (FIFO)
    • Least recently used elimination algorithm (LRU)
  • Among them, the highest average hit rate is the LRU algorithm

1.5. Cache memory write operation

  • When using Cache, you need to ensure that its data is consistent with the main memory. Therefore, you must consider the synchronization with the main memory when writing to the Cache. The following three methods are usually used:
    • Direct write: When the Cache write hits, the Cache and the main memory write modification at the same time
    • Write back: When the CPU writes to the Cache, only the content of the Cache is modified and not written to the main memory immediately, and the line is written back to the main memory when the line is swapped out
    • Notation: After the data enters the Cache, the effective position is 1; when the CPU modifies the data, the data is only written to the main memory and the effective position is 0. When data is to be read from the Cache, the effective position should be tested. If it is 1, it will fetch the data directly from the Cache, otherwise it will fetch the data from the main memory.